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ISCA
2009
IEEE
153views Hardware» more  ISCA 2009»
13 years 10 months ago
Indirect adaptive routing on large scale interconnection networks
Nan Jiang, John Kim, William J. Dally
ISCA
2009
IEEE
143views Hardware» more  ISCA 2009»
13 years 10 months ago
Spatio-temporal memory streaming
Recent research advocates memory streaming techniques to alleviate the performance bottleneck caused by the high latencies of off-chip memory accesses. Temporal memory streaming r...
Stephen Somogyi, Thomas F. Wenisch, Anastasia Aila...
ISCA
2009
IEEE
173views Hardware» more  ISCA 2009»
13 years 10 months ago
A fault tolerant, area efficient architecture for Shor's factoring algorithm
Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh...
ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
13 years 10 months ago
Hardware support for WCET analysis of hard real-time multicore systems
Marco Paolieri, Eduardo Quiñones, Francisco...
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
13 years 10 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
13 years 10 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
ISCA
2009
IEEE
230views Hardware» more  ISCA 2009»
13 years 10 months ago
Architecting phase change memory as a scalable dram alternative
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM)...
Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burg...
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
13 years 10 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
ISCA
2009
IEEE
150views Hardware» more  ISCA 2009»
13 years 10 months ago
Stream chaining: exploiting multiple levels of correlation in data prefetching
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
Pedro Diaz, Marcelo Cintra