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ISCA
2012
IEEE
242views Hardware» more  ISCA 2012»
7 years 10 months ago
Side-channel vulnerability factor: A metric for measuring information leakage
There have been many attacks that exploit side-effects of program execution to expose secret information and many proposed countermeasures to protect against these attacks. Howeve...
John Demme, Robert Martin, Adam Waksman, Simha Set...
ISCA
2012
IEEE
248views Hardware» more  ISCA 2012»
7 years 10 months ago
Watchdog: Hardware for safe and secure manual memory management and full memory safety
Languages such as C and C++ use unsafe manual memory management, allowing simple bugs (i.e., accesses to an object after deallocation) to become the root cause of exploitable secu...
Santosh Nagarakatte, Milo M. K. Martin, Steve Zdan...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
7 years 10 months ago
The Yin and Yang of power and performance for asymmetric hardware and managed software
Ting Cao, Stephen M. Blackburn, Tiejun Gao, Kathry...
ISCA
2012
IEEE
280views Hardware» more  ISCA 2012»
7 years 10 months ago
A case for random shortcut topologies for HPC interconnects
—As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance C...
Michihiro Koibuchi, Hiroki Matsutani, Hideharu Ama...
ISCA
2012
IEEE
212views Hardware» more  ISCA 2012»
7 years 10 months ago
TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks
Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on ...
Robert Martin, John Demme, Simha Sethumadhavan
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
7 years 10 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
7 years 10 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
7 years 10 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
ISCA
2012
IEEE
233views Hardware» more  ISCA 2012»
7 years 10 months ago
iGPU: Exception support and speculative execution on GPUs
Jaikrishnan Menon, Marc de Kruijf, Karthikeyan San...
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
7 years 10 months ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...
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