ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along th...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
—In this paper we propose an analog VLSI approach to maximum a posteriori (MAP) detection in Multiple-Input Multiple-Output (MIMO) systems. This detector can be seen as an extens...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
—This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of C...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— an efficient rate-distortion (R-D) optimal method for transcoding hierarchical B-pictures is proposed in this paper. A new R-D model is presented for fast transcoding hierarchi...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...