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ISLPED
1995
ACM
125views Hardware» more  ISLPED 1995»
11 years 9 months ago
Transforming set data types to power optimal data structures
In this paper we present a novel approach to model the search space for optimal set data types in network component realisations. The main objective is to arrive at power efficie...
Sven Wuytack, Francky Catthoor, Hugo De Man
ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
11 years 9 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
ISLPED
1995
ACM
114views Hardware» more  ISLPED 1995»
11 years 9 months ago
Power and area optimization by reorganizing CMOS complex gate circuits
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
11 years 9 months ago
Logic design for low-voltage/low-power CMOS circuits
Christian Piguet, Jean-Marc Masgonty, V. von Kaene...
ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
11 years 9 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...
ISLPED
1995
ACM
122views Hardware» more  ISLPED 1995»
11 years 9 months ago
A multiple clocking scheme for low power RTL design
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
Christos A. Papachristou, Mark Spining, Mehrdad No...
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
11 years 9 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
11 years 9 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
ISLPED
1995
ACM
103views Hardware» more  ISLPED 1995»
11 years 9 months ago
Information theoretic measures of energy consumption at register transfer level
- The problem of estimating the energy consumption at register transfer level is addressed from an information theoretical point of view. It is shown that the average switching act...
Diana Marculescu, Radu Marculescu, Massoud Pedram
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