Sciweavers

ISMVL
2007
IEEE
76views Hardware» more  ISMVL 2007»
13 years 11 months ago
Variable Reordering and Sifting for QMDD
This paper considers variable reordering for quantum multiple-valued decision diagrams (QMDD) used to represent the matrices describing reversible and quantum gates and circuits. ...
D. Michael Miller, David Y. Feinstein, Mitchell A....
ISMVL
2007
IEEE
109views Hardware» more  ISMVL 2007»
13 years 11 months ago
Quantum Mechanical Model of Emotional Robot Behaviors
In this paper the emotional model of the humanoid Cynthea (Cybernetic Networked Humanoid Emotional Agent) robot is presented. The robot is explained at two levels: the cognitive l...
Martin Lukac, Marek A. Perkowski
ISMVL
2007
IEEE
100views Hardware» more  ISMVL 2007»
13 years 11 months ago
A Complete Resolution Calculus for Signed Max-SAT
We define a resolution-style rule for solving the Max-SAT problem of Signed CNF formulas (Signed Max-SAT) and prove that our rule provides a complete calculus for that problem. F...
Carlos Ansótegui, Maria Luisa Bonet, Jordi ...
ISMVL
2007
IEEE
90views Hardware» more  ISMVL 2007»
13 years 11 months ago
Quantum Robots for Teenagers
Extending the ideas of Quantum Braitenberg Vehicles from [14], we present here a family of Lego robots controlled by multiple-valued quantum circuits. The robots have at most 6 de...
Arushi Raghuvanshi, Yale Fan, Michal Woyke, Marek ...
ISMVL
2007
IEEE
245views Hardware» more  ISMVL 2007»
13 years 11 months ago
Fault Tolerant CMOS Logic Using Ternary Gates
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
Yngvar Berg, Renè Jensen, Johannes Goplen L...
ISMVL
2007
IEEE
95views Hardware» more  ISMVL 2007»
13 years 11 months ago
Simulation of Gate Circuits with Feedback in Multi-Valued Algebras
Simulation of gate circuits is an efficient method of detecting hazards and oscillations that may occur because of delays. Ternary simulation consists of two algorithms, A and B,...
Janusz A. Brzozowski, Yuli Ye
ISMVL
2007
IEEE
106views Hardware» more  ISMVL 2007»
13 years 11 months ago
Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices
This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circui...
Henning Gundersen, Yngvar Berg