ISPD
1997
ACM
13 years 8 months ago
1997
ACM
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
In a typical VLSI/PCB design, some modules are pre-placed in advance, and the other modules are requested to be placed without overlap with these pre-placed modules. The presence ...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
We present results which show that a separate global and detailed routing strategy can be competitive with a combined routing process. Under restricted architectural assumptions, ...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM
— In this paper, we consider the thermal placement problem for gate arrays. We introduce a new combinatorial optimization problem, matrix synthesis problem (MSP), to model the th...
ISPD
1997
ACM
13 years 8 months ago
1997
ACM