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DAC
2012
ACM
9 years 4 months ago
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Myung-Chul Kim, Igor L. Markov
ISPD
2012
ACM
234views Hardware» more  ISPD 2012»
9 years 9 months ago
MAPLE: multilevel adaptive placement for mixed-size designs
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
Myung-Chul Kim, Natarajan Viswanathan, Charles J. ...
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
11 years 7 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ISPD
2005
ACM
123views Hardware» more  ISPD 2005»
11 years 7 months ago
FastPlace: an analytical placer for mixed-mode designs
Natarajan Viswanathan, Min Pan, Chris C. N. Chu
ISPD
2005
ACM
185views Hardware» more  ISPD 2005»
11 years 7 months ago
Dragon2005: large-scale mixed-size placement tool
In this paper, we develop a mixed-size placement tool, Dragon2005, to solve large scale placement problems effectively. A top-down hierarchical approach based on min-cut partition...
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi
ISPD
2005
ACM
221views Hardware» more  ISPD 2005»
11 years 7 months ago
Kraftwerk: a versatile placement approach
During the ispd05 placement contest, we employed the forcedirected approach Kraftwerk for global placement complemented by the network-flow based final placer Domino. These powe...
Bernd Obermeier, Hans Ranke, Frank M. Johannes
ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
11 years 7 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
ISPD
2005
ACM
126views Hardware» more  ISPD 2005»
11 years 7 months ago
Effects of on-chip inductance on power distribution grid
With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We pe...
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi O...
ISPD
2005
ACM
168views Hardware» more  ISPD 2005»
11 years 7 months ago
Capo: robust and scalable open-source min-cut floorplacer
In this invited note we describe Capo, an open-source software tool for cell placement, mixed-size placement and floorplanning with emphasis on routability. Capo is among the fas...
Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hay...
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
11 years 7 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu
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