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ISPD
2009
ACM
91views Hardware» more  ISPD 2009»
12 years 8 months ago
A metal-only-ECO solver for input-slew and output-loading violations
Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo,...
ISPD
2009
ACM
127views Hardware» more  ISPD 2009»
12 years 8 months ago
Synthesizing a representative critical path for post-silicon delay prediction
Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit a...
Qunzeng Liu, Sachin S. Sapatnekar
ISPD
2009
ACM
297views Hardware» more  ISPD 2009»
12 years 8 months ago
Physical optimization for FPGAs using post-placement topology rewriting
Val Pevzner, Andrew A. Kennings, Andy Fox
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
12 years 8 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ISPD
2009
ACM
126views Hardware» more  ISPD 2009»
12 years 8 months ago
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
Yifang Liu, Jiang Hu
ISPD
2009
ACM
127views Hardware» more  ISPD 2009»
12 years 8 months ago
Multi-voltage floorplan design with optimal voltage assignment
Qian Zaichen, Evangeline F. Y. Young
ISPD
2009
ACM
74views Hardware» more  ISPD 2009»
12 years 8 months ago
Transistor-level layout of high-density regular circuits
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Ma...
ISPD
2009
ACM
118views Hardware» more  ISPD 2009»
12 years 8 months ago
Wire shaping is practical
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Li...
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