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ISQED
2003
IEEE
233views Hardware» more  ISQED 2003»
10 years 3 months ago
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-...
Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
ISQED
2003
IEEE
73views Hardware» more  ISQED 2003»
10 years 3 months ago
A Novel Clocking Strategy for Dynamic Circuits
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
ISQED
2003
IEEE
96views Hardware» more  ISQED 2003»
10 years 3 months ago
Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint
Mind-boggling complexity of EDA tools necessitates reuse of intellectual property in any large-scale commercial or academic operation. However, due to the nature of software, a to...
Andrew B. Kahng, Igor L. Markov
ISQED
2003
IEEE
96views Hardware» more  ISQED 2003»
10 years 3 months ago
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, D...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
10 years 3 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
ISQED
2003
IEEE
303views Hardware» more  ISQED 2003»
10 years 3 months ago
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
Payam Heydari
ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
10 years 3 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
ISQED
2003
IEEE
71views Hardware» more  ISQED 2003»
10 years 3 months ago
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
10 years 3 months ago
Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing
The nature of IC design has is necessarily evolving to a more data-centric design flow in which EDA tools share a common information in a design database without the negative cost...
D. R. Cottrell, T. J. Grebinski
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