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ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
11 years 4 months ago
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
Hao Yu, Lei He
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
11 years 4 months ago
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
11 years 4 months ago
An ILP Formulation for Reliability-Oriented High-Level Synthesis
Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulatio...
Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Er...
ISQED
2005
IEEE
128views Hardware» more  ISQED 2005»
11 years 4 months ago
Reliability-Centric Hardware/Software Co-Design
This paper proposes a reliability-centric hardware/ software co-design framework. This framework operates with a component library that provides multiple alternates for a given ta...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...
ISQED
2005
IEEE
112views Hardware» more  ISQED 2005»
11 years 4 months ago
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
Layout migration has re-emerged as an important task due to the increasing use of library hard intellectual properties. While recent advances of migration tools have accommodated ...
Qianying Tang, Jianwen Zhu
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
11 years 4 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
11 years 4 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
11 years 4 months ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...
ISQED
2005
IEEE
162views Hardware» more  ISQED 2005»
11 years 4 months ago
Controlled-Load Limited Switch Dynamic Logic Circuit
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
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