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ISQED
2006
IEEE
85views Hardware» more  ISQED 2006»
10 years 1 months ago
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze T...
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
10 years 1 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
10 years 1 months ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...
ISQED
2006
IEEE
259views Hardware» more  ISQED 2006»
10 years 1 months ago
Impact of NBTI on SRAM Read Stability and Design for Reliability
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
ISQED
2006
IEEE
147views Hardware» more  ISQED 2006»
10 years 1 months ago
Compact Reduced Order Modeling for Multiple-Port Interconnects
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng ...
ISQED
2006
IEEE
132views Hardware» more  ISQED 2006»
10 years 1 months ago
Leakage Biased Sleep Switch Domino Logic
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
Zhiyu Liu, Volkan Kursun
ISQED
2006
IEEE
176views Hardware» more  ISQED 2006»
10 years 1 months ago
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
Zhiyu Liu, Volkan Kursun
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
10 years 1 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
ISQED
2006
IEEE
89views Hardware» more  ISQED 2006»
10 years 1 months ago
Study of Floating Fill Impact on Interconnect Capacitance
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
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