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ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
11 years 11 months ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
ISQED
2008
IEEE
142views Hardware» more  ISQED 2008»
11 years 11 months ago
Clock Skew Analysis via Vector Fitting in Frequency Domain
An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and...
Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang,...
ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
11 years 11 months ago
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates
— The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as comp...
Emre Salman, Eby G. Friedman, Radu M. Secareanu, O...
ISQED
2008
IEEE
119views Hardware» more  ISQED 2008»
11 years 11 months ago
Instruction Scheduling for Variation-Originated Variable Latencies
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variat...
Toshinori Sato, Shingo Watanabe
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
11 years 11 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ISQED
2008
IEEE
101views Hardware» more  ISQED 2008»
11 years 11 months ago
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
Xin Li, Yu Cao
ISQED
2008
IEEE
124views Hardware» more  ISQED 2008»
11 years 11 months ago
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
ISQED
2008
IEEE
112views Hardware» more  ISQED 2008»
11 years 11 months ago
Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...
Udo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael ...
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
11 years 11 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
ISQED
2008
IEEE
115views Hardware» more  ISQED 2008»
11 years 11 months ago
Elastic Timing Scheme for Energy-Efficient and Robust Performance
Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Ji...
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