Sciweavers

ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 2 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
13 years 3 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
ISQED
2010
IEEE
127views Hardware» more  ISQED 2010»
13 years 3 months ago
Limits of bias based assist methods in nano-scale 6T SRAM
Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRA...
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Bent...
ISQED
2010
IEEE
133views Hardware» more  ISQED 2010»
13 years 3 months ago
UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...
Shirish Bahirat, Sudeep Pasricha
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
13 years 6 months ago
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
Jun Zhao, Yong-Bin Kim
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
13 years 6 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 6 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
13 years 6 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
13 years 6 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
ISQED
2010
IEEE
161views Hardware» more  ISQED 2010»
13 years 6 months ago
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedr...