ISSS
1998
IEEE
13 years 8 months ago
1998
IEEE
Commonly used scheduling algorithms in high-level synthesis are not capable of sharing resources across process boundaries. This results in the usage of at least one resource per ...
ISSS
1998
IEEE
13 years 8 months ago
1998
IEEE
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
ISSS
1998
IEEE
13 years 8 months ago
1998
IEEE
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
ISSS
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
ISSS
1998
IEEE
13 years 8 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...