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    ISVLSI
    2002
    IEEE
    91views VLSI» more  ISVLSI 2002»
    Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
    13 years 9 months ago
    Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
    Download  www.ece.msstate.edu
    J. W. Bruce, Mitchell A. Thornton, L. Shivakumarai...
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    ISVLSI
    2002
    IEEE
    129views VLSI» more  ISVLSI 2002»
    Accelerating Retiming Under the Coupled-Edge Timing Model
    13 years 9 months ago
    Accelerating Retiming Under the Coupled-Edge Timing Model
    Download  eis.eit.uni-kl.de
    Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
    Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
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