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ISVLSI
2007
IEEE
139views VLSI» more  ISVLSI 2007»
10 years 10 months ago
Automatic Retargeting of Binary Utilities for Embedded Code Generation
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
Alexandro Baldassin, Paulo Centoducatte, Sandro Ri...
ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
10 years 10 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
10 years 10 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
ISVLSI
2007
IEEE
205views VLSI» more  ISVLSI 2007»
10 years 10 months ago
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
Angan Das, Ranga Vemuri
ISVLSI
2007
IEEE
194views VLSI» more  ISVLSI 2007»
10 years 10 months ago
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
Ewerson Carvalho, Ney Laert Vilar Calazans, Fernan...
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
10 years 10 months ago
A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions
This paper presents a quantum algorithm for finding minimal ESCT (Exclusive-or Sum of Complex Terms) or ESOP (Exclusiveor Sum Of Products) expressions for any arbitrary incomplet...
Marinos Sampson, Dimitrios Voudouris, George K. Pa...
ISVLSI
2007
IEEE
126views VLSI» more  ISVLSI 2007»
10 years 10 months ago
MOTIM - A Scalable Architecture for Ethernet Switches
Erico Bastos, Everton Carara, Daniel V. Pigatto, N...
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
10 years 10 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
10 years 10 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
10 years 10 months ago
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...
Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
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