Sciweavers

ISVLSI
2007
IEEE
161views VLSI» more  ISVLSI 2007»
13 years 10 months ago
CMP-aware Maze Routing Algorithm for Yield Enhancement
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
Hailong Yao, Yici Cai, Xianlong Hong
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...
ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...
ISVLSI
2007
IEEE
100views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Vector Processing Support for FPGA-Oriented High Performance Applications
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor suppor...
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie...
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
ISVLSI
2007
IEEE
160views VLSI» more  ISVLSI 2007»
13 years 10 months ago
On the Limitations of Power Macromodeling Techniques
Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as ...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
ISVLSI
2007
IEEE
107views VLSI» more  ISVLSI 2007»
13 years 10 months ago
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of ion. A possible sol...
Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide P...
ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
13 years 10 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz