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ISVLSI
2008
IEEE
191views VLSI» more  ISVLSI 2008»
8 years 9 months ago
NoC Power Estimation at the RTL Abstraction Level
Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp...
ISVLSI
2008
IEEE
140views VLSI» more  ISVLSI 2008»
8 years 9 months ago
A Versatile Linear Insertion Sorter Based on a FIFO Scheme
Roberto Perez-Andrade, René Cumplido, Ferna...
ISVLSI
2008
IEEE
152views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...
Julien Dalmasso, Érika F. Cota, Marie-Lise ...
ISVLSI
2008
IEEE
125views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Energy Recovery from High-Frequency Clocks Using DC-DC Converters
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Sha...
ISVLSI
2008
IEEE
188views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Defect Tolerance Inspired by Artificial Evolution
Asbjørn Djupdal, Pauline C. Haddow
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
8 years 9 months ago
CMOS Control Enabled Single-Type FET NASIC
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
Pritish Narayanan, Michael Leuchtenburg, Teng Wang...
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
8 years 9 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
8 years 9 months ago
Characterisation of FPGA Clock Variability
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...
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