Sciweavers

ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
ISVLSI
2008
IEEE
126views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Run...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistor...
Maziar Goudarzi, Tadayuki Matsumura, Tohru Ishihar...
ISVLSI
2008
IEEE
161views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Impact of Technology Scaling on Digital Subthreshold Circuits
Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circ...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
ISVLSI
2008
IEEE
129views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices
The number of edge devices connected to the Internet is increasing at a rapid rate. To maintain network connectivity, the majority of these devices remain completely powered on wh...
Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden...
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
13 years 10 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods...
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha...
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
13 years 10 months ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
ISVLSI
2008
IEEE
118views VLSI» more  ISVLSI 2008»
13 years 10 months ago
MPI-Based Adaptive Task Migration Support on the HS-Scale System
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...
Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatel...
ISVLSI
2008
IEEE
149views VLSI» more  ISVLSI 2008»
13 years 10 months ago
Uncriticality-Directed Low-Power Instruction Scheduling
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
Shingo Watanabe, Toshinori Sato