ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that runlength c...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that h...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
A two-wire test strategy with simultaneous bidirectional data flow and an independent clock line enables very high site count low-cost wafer probing.
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...