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ITC
2003
IEEE
146views Hardware» more  ITC 2003»
9 years 5 months ago
A New Approach for Low Power Scan Testing
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
Takaki Yoshida, Masafumi Watari
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
9 years 5 months ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
ITC
2003
IEEE
143views Hardware» more  ITC 2003»
9 years 5 months ago
Designed -in-diagnostics: A new optical method
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
Keneth R. Wilsher
ITC
2003
IEEE
93views Hardware» more  ITC 2003»
9 years 5 months ago
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing
Motivated by the increasing area and performance overhead caused by wrapping the embedded cores for modular SOC testing, this paper proposes a solution for reducing the number of ...
Qiang Xu, Nicola Nicolici
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
9 years 5 months ago
A Hybrid Coding Strategy For Optimized Test Data Compression
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that runlength c...
Armin Würtenberger, Christofer S. Tautermann,...
ITC
2003
IEEE
136views Hardware» more  ITC 2003»
9 years 5 months ago
Adapting JTAG for AC Interconnect Testing
The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that h...
Lee Whetsel
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
9 years 5 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
ITC
2003
IEEE
113views Hardware» more  ITC 2003»
9 years 5 months ago
Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy
A two-wire test strategy with simultaneous bidirectional data flow and an independent clock line enables very high site count low-cost wafer probing.
Burnell G. West
ITC
2003
IEEE
153views Hardware» more  ITC 2003»
9 years 5 months ago
An Efficient and Effective Methodology on the Multiple Fault Diagnosis
In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient...
Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadow...
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
9 years 5 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
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