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ITC
2003
IEEE
147views Hardware» more  ITC 2003»
13 years 9 months ago
The Testability Features of The ARM1026EJ Microprocessor Core
The DFT and Test challenges faced, and the solutions applied, to the ARM1026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the...
Teresa L. McLaurin, Frank Frederick, Rich Slobodni...
ITC
2003
IEEE
118views Hardware» more  ITC 2003»
13 years 9 months ago
Method of reducing contactor effect when testing high-precision ADCs
— Being able to test the intrinsic performance of a device under test (DUT) has always been the main goal of a test engineer. Achieving this goal is becoming increasingly diffic...
Gwenolé Maugard, Carsten Wegener, Tom O'Dwy...
ITC
2003
IEEE
145views Hardware» more  ITC 2003»
13 years 9 months ago
MEMS Manufacturing Testing: An Accelerometer Case Study
Electrical testing of MicroElectroMechanical Systems (MEMS) can take on many different forms including wafer probing, electrical trimming, final test at temperatures, engineering ...
Theresa Maudie, Alex Hardt, Rick Nielsen, Dennis S...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
13 years 9 months ago
Deformations of IC Structure in Test and Yield Learning
This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Tr...
Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Tho...
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
13 years 9 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
ITC
2003
IEEE
168views Hardware» more  ITC 2003»
13 years 9 months ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
13 years 9 months ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
13 years 9 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
ITC
2003
IEEE
104views Hardware» more  ITC 2003»
13 years 9 months ago
On-line Detection of Faults in Carry-Select Adders
This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to ...
B. Kiran Kumar, Parag K. Lala