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MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
10 years 5 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
HPCA
2007
IEEE
10 years 6 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The signi´Čücant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
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