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LCTRTS
2001
Springer
13 years 9 months ago
Automatic Accurate Live Memory Analysis for Garbage-Collected Languages
Leena Unnikrishnan, Scott D. Stoller, Yanhong A. L...
LCTRTS
2001
Springer
13 years 9 months ago
Combining Global Code and Data Compaction
Computers are increasingly being incorporated in devices with a limited amount of available memory. As a result research is increasingly focusing on the automated reduction of pro...
Bjorn De Sutter, Bruno De Bus, Koenraad De Bossche...
LCTRTS
2001
Springer
13 years 9 months ago
Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA
Strict control over the scheduling and execution of processor resources is essential for many fixed-priority real-time applications. To facilitate this common requirement, the Re...
Irfan Pyarali, Marina Spivak, Ron Cytron, Douglas ...
LCTRTS
2001
Springer
13 years 9 months ago
Middleware For Building Adaptive Systems Via Configuration
1 COTS (commercial off-the-shelf) devices are capable of executing powerful, distributed algorithms. Very large, adaptive systems can be created by simply integrating these devices...
Sanjai Narain, Ravichander Vaidyanathan, Stanley M...
LCTRTS
2001
Springer
13 years 9 months ago
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors
Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naeh...
LCTRTS
2001
Springer
13 years 9 months ago
Embedded Control Systems Development with Giotto
Giotto is a principled, tool-supported design methodology for implementing embedded control systems on platforms of possibly distributed sensors, actuators, CPUs, and networks. Gio...
Thomas A. Henzinger, Benjamin Horowitz, Christoph ...
LCTRTS
2001
Springer
13 years 9 months ago
A Dynamic Programming Approach to Optimal Integrated Code Generation
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
Christoph W. Keßler, Andrzej Bednarski
LCTRTS
2001
Springer
13 years 9 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel