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LCTRTS
2007
Springer
9 years 6 months ago
On the complexity of spill everywhere under SSA form
Florent Bouchez, Alain Darte, Fabrice Rastello
LCTRTS
2007
Springer
9 years 6 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...
LCTRTS
2007
Springer
9 years 6 months ago
Hierarchical real-time garbage collection
Memory management is a critical issue for correctness and performance in real-time embedded systems. Recent work on real-time garbage collectors has shown that it is possible to p...
Filip Pizlo, Antony L. Hosking, Jan Vitek
LCTRTS
2007
Springer
9 years 6 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski
LCTRTS
2007
Springer
9 years 6 months ago
Dynamic data scratchpad memory management for a memory subsystem with an MMU
Hyungmin Cho, Bernhard Egger, Jaejin Lee, Heonshik...
LCTRTS
2007
Springer
9 years 6 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
LCTRTS
2007
Springer
9 years 6 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
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