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TCAD
2002
134views more  TCAD 2002»
13 years 3 months ago
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
Seongmoon Wang, Sandeep K. Gupta
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
13 years 9 months ago
A highly regular multi-phase reseeding technique for scan-based BIST
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
FSE
2004
Springer
84views Cryptology» more  FSE 2004»
13 years 9 months ago
Vulnerability of Nonlinear Filter Generators Based on Linear Finite State Machines
We present a realization of an LFSM that utilizes an LFSR. This is based on a well-known fact from linear algebra. This structure is used to show that a previous attempt at using a...
Jin Hong, Dong Hoon Lee 0002, Seongtaek Chee, Pala...
IPPS
2007
IEEE
13 years 10 months ago
From Hardware to Software Synthesis of Linear Feedback Shift Registers
Linear Feedback Shift Registers (LFSRs) have always received considerable attention in computer science especially in coding theory and in cryptography. The scope of applications ...
Cédric Lauradoux
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
13 years 10 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...