TC
2002
13 years 4 months ago
2002
MICRO
1995
IEEE
13 years 7 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
ISCA
1999
IEEE
13 years 8 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
IPPS
2003
IEEE
13 years 9 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
IISWC
2006
IEEE
13 years 10 months ago
2006
IEEE
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...