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TC
1998
13 years 4 months ago
Using Decision Diagrams to Design ULMs for FPGAs
—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possib...
Zeljko Zilic, Zvonko G. Vranesic
FPGA
2008
ACM
170views FPGA» more  FPGA 2008»
13 years 6 months ago
Architecture-specific packing for virtex-5 FPGAs
We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA
Taneem Ahmed, Paul D. Kundarewich, Jason Helge And...
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
13 years 8 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
13 years 8 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
FPL
2009
Springer
99views Hardware» more  FPL 2009»
13 years 9 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FPL
2005
Springer
114views Hardware» more  FPL 2005»
13 years 10 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
13 years 10 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
ICCD
2004
IEEE
137views Hardware» more  ICCD 2004»
14 years 1 months ago
Comparative Study of Strategies for Formal Verification of High-Level Processors
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...
Miroslav N. Velev