Sciweavers

ETS
2011
IEEE
230views Hardware» more  ETS 2011»
12 years 4 months ago
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak,...
TODAES
2002
134views more  TODAES 2002»
13 years 4 months ago
False-noise analysis using logic implications
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...
DATE
2000
IEEE
87views Hardware» more  DATE 2000»
13 years 8 months ago
Multi-Node Static Logic Implications for Redundancy Identification
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
Kabir Gulrajani, Michael S. Hsiao
GLVLSI
2010
IEEE
178views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Improving the testability and reliability of sequential circuits with invariant logic
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
ICCD
2005
IEEE
135views Hardware» more  ICCD 2005»
14 years 1 months ago
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults
In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Using a nove...
Manan Syal, Rajat Arora, Michael S. Hsiao