Sciweavers

ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
13 years 1 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
ICCAD
1998
IEEE
101views Hardware» more  ICCAD 1998»
13 years 7 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
13 years 8 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska