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TABLEAUX
2000
Springer
13 years 7 months ago
Benchmark Analysis with FaCT
FaCT (Fast Classification of Terminologies) is a Description Logic (DL) classifier that can also be used for modal logic satisfiability testing. The FaCT system includes two reason...
Ian Horrocks
ARVLSI
1995
IEEE
220views VLSI» more  ARVLSI 1995»
13 years 7 months ago
Optimization of combinational and sequential logic circuits for low power using precomputation
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
José Monteiro, John Rinderknecht, Srinivas ...
FOSSACS
2006
Springer
13 years 7 months ago
A Logic of Reachable Patterns in Linked Data-Structures
We define a new decidable logic for expressing and checking invariants of programs that manipulate dynamically-allocated objects via pointers and destructive pointer updates. The ...
Greta Yorsh, Alexander Moshe Rabinovich, Mooly Sag...
FORMATS
2006
Springer
13 years 7 months ago
A Dose of Timed Logic, in Guarded Measure
We consider interval measurement logic IML, a sublogic of Zhou and Hansen's interval logic, with measurement functions which provide real-valued measurement of some aspect of ...
Kamal Lodaya, Paritosh K. Pandya
ESORICS
2006
Springer
13 years 7 months ago
A Linear Logic of Authorization and Knowledge
We propose a logic for specifying security policies at a very el of abstraction. The logic accommodates the subjective nature of affirmations for authorization and knowledge withou...
Deepak Garg, Lujo Bauer, Kevin D. Bowers, Frank Pf...
ESOP
2006
Springer
13 years 7 months ago
ILC: A Foundation for Automated Reasoning About Pointer Programs
This paper presents a new program logic designed for facilitating automated reasoning about pointer programs. The program logic is directly inspired by previous work by O'Hea...
Limin Jia, David Walker
CSR
2006
Springer
13 years 7 months ago
Logic of Proofs for Bounded Arithmetic
The logic of proofs is known to be complete for the semantics of proofs in PA. In this paper we present a refinement of this theorem, we will show that we can assure that all the ...
Evan Goris
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
13 years 7 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
13 years 7 months ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
13 years 7 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki