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DATE
2000
IEEE
108views Hardware» more  DATE 2000»
13 years 9 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
GLOBECOM
2006
IEEE
13 years 11 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...