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    ARITH
    2005
    IEEE
    137views Applied Computing» more  ARITH 2005»
    Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
    13 years 11 months ago
    Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
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    In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
    Javier D. Bruguera, Tomás Lang
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