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MEMOCODE
2007
IEEE
10 years 7 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
MEMOCODE
2007
IEEE
10 years 7 months ago
Software/Hardware Engineering with the Parallel Object-Oriented Specification Language
Bart D. Theelen, Oana Florescu, Marc Geilen, Jinfe...
MEMOCODE
2007
IEEE
10 years 7 months ago
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
Orthogonal Frequency-Division Multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral...
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Da...
MEMOCODE
2007
IEEE
10 years 7 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...
MEMOCODE
2007
IEEE
10 years 7 months ago
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA
Nirav Dave, Kermin Fleming, Myron King, Michael Pe...
MEMOCODE
2007
IEEE
10 years 7 months ago
MEMOCODE 2007 Co-Design Contest
New to the 2007 MEMOCODE conference is the HW/SW Co-Design Contest. Members of the technical and steering committees from MEMOCODE 2006 thought that the co-design practice is dist...
Forrest Brewer, James C. Hoe
MEMOCODE
2007
IEEE
10 years 7 months ago
VT Matrix Multiply Design for MEMOCODE '07
This design presents a system optimized for complex matrix multiplications on the XUP Virtex-II board. Utilizing the GEZEL HW/SW co-simulation environment, the resulting system ac...
Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumi...
MEMOCODE
2007
IEEE
10 years 7 months ago
Towards Equivalence Checking Between TLM and RTL Models
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
Nicola Bombieri, Franco Fummi, Graziano Pravadelli...
MEMOCODE
2007
IEEE
10 years 7 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
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