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    CORR
    2006
    Springer
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    High-level synthesis under I/O Timing and Memory constraints
    13 years 4 months ago
    High-level synthesis under I/O Timing and Memory constraints
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    The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
    Philippe Coussy, Gwenolé Corre, Pierre Bome...
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