Sciweavers

ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
13 years 9 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...