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TJS
2008
95views more  TJS 2008»
13 years 4 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
MAM
2006
92views more  MAM 2006»
13 years 4 months ago
A high throughput 3D-bus interconnect for network processors
Deep layer processing and increasing line rates present a memory challenge to processor
Taskin Koçak, Jacob Engel
CDES
2006
89views Hardware» more  CDES 2006»
13 years 5 months ago
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability
Memory accesses have always been a speed-limiting factor, and memory bandwidth has always been an intensively contended scarce resource. Nevertheless, with recent pervasive emergen...
Hui-Chin Yang, Chung-Ping Chung
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 6 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
13 years 8 months ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross
HPCA
1995
IEEE
13 years 8 months ago
Access Ordering and Memory-Conscious Cache Utilization
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance factor for many applications. Several approaches to bridging ...
Sally A. McKee, William A. Wulf
HPCA
1995
IEEE
13 years 8 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
13 years 8 months ago
HINT: A new way to measure computer performance
The computing community has long faced the problem of scientifically comparing different computers and different algorithms. When architecture, method, precision, or storage capac...
John L. Gustafson, Quinn Snell
EUROPAR
1995
Springer
13 years 8 months ago
Bounds on Memory Bandwidth in Streamed Computations
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance ga...
Sally A. McKee, William A. Wulf, Trevor C. Landon
CODES
2004
IEEE
13 years 8 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...