Sciweavers

    PVLDB
    2010
    90views more  PVLDB 2010»
    The HV-tree: a Memory Hierarchy Aware Version Index
    13 years 2 months ago
    The HV-tree: a Memory Hierarchy Aware Version Index
    Download  www.comp.nus.edu.sg
    The huge amount of temporal data generated from many important applications call for a highly efficient and scalable version index. The TSB-tree has the potential of large scalab...
    Rui Zhang, Martin Stradling
    claim paper
    Read More »
    JCSC
    2002
    87views more  JCSC 2002»
    Power Estimator Development for Embedded System Memory Tuning
    13 years 4 months ago
    Power Estimator Development for Embedded System Memory Tuning
    Download  www.cs.ucr.edu
    Memory accesses account for a large percentage of total power in microprocessor-based embedded systems. The increasing use of microprocessor cores and synthesis, rather than prefa...
    Frank Vahid, Tony Givargis, Susan Cotterell
    claim paper
    Read More »
    VLSISP
    2008
    95views more  VLSISP 2008»
    Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
    13 years 4 months ago
    Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
    Download  www.si2lab.org
    This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
    Tsu-Ming Liu, Chen-Yi Lee
    claim paper
    Read More »
    ISCAPDCS
    2004
    153views Distributed And Parallel Com...» more  ISCAPDCS 2004»
    FG: A Framework Generator for Hiding Latency in Parallel Programs Running on Clusters
    13 years 6 months ago
    FG: A Framework Generator for Hiding Latency in Parallel Programs Running on Clusters
    Download  www.cs.dartmouth.edu
    FG is a programming environment for asynchronous programs that run on clusters and fit into a pipeline framework. It enables the programmer to write a series of synchronous functi...
    Thomas H. Cormen, Elena Riccio Davidson
    claim paper
    Read More »
    CIDR
    2007
    144views Algorithms» more  CIDR 2007»
    Cache-Oblivious Query Processing
    13 years 6 months ago
    Cache-Oblivious Query Processing
    Download  www-db.cs.wisc.edu
    We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...
    Bingsheng He, Qiong Luo
    claim paper
    Read More »
    DAMON
    2008
    Springer
    159views Information Technology» more  DAMON 2008»
    Avoiding version redundancy for high performance reads in temporal databases
    13 years 6 months ago
    Avoiding version redundancy for high performance reads in temporal databases
    Download  www.cse.ust.hk
    A major performance bottleneck for database systems is the memory hierarchy. The performance of the memory hierarchy is directly related to how the content of disk pages maps to t...
    Khaled Jouini, Geneviève Jomier
    claim paper
    Read More »
    EXPCS
    2007
    142views Theoretical Computer Science» more  EXPCS 2007»
    Pipeline spectroscopy
    13 years 6 months ago
    Pipeline spectroscopy
    Download  www.usenix.org
    Pipeline Spectroscopy is a new technique that allows us to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogram, which represents a precis...
    Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...
    claim paper
    Read More »
    ISCA
    1997
    IEEE
    93views Hardware» more  ISCA 1997»
    The Energy Efficiency of IRAM Architectures
    13 years 8 months ago
    The Energy Efficiency of IRAM Architectures
    Download  csl.stanford.edu
    Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
    Richard Fromm, Stylianos Perissakis, Neal Cardwell...
    claim paper
    Read More »
    MICRO
    2000
    IEEE
    121views Hardware» more  MICRO 2000»
    Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
    13 years 8 months ago
    Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
    Download  www.ece.rochester.edu
    Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
    Rajeev Balasubramonian, David H. Albonesi, Alper B...
    claim paper
    Read More »
    DATE
    2004
    IEEE
    119views Hardware» more  DATE 2004»
    Using a Victim Buffer in an Application-Specific Memory Hierarchy
    13 years 8 months ago
    Using a Victim Buffer in an Application-Specific Memory Hierarchy
    Download  www.cs.ucr.edu
    Chuanjun Zhang, Frank Vahid
    claim paper
    Read More »
    « first‹ previous12345next ›last »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.