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DATE
2010
IEEE
202views Hardware» more  DATE 2010»
13 years 9 months ago
FlashPower: A detailed power model for NAND flash memory
Abstract— Flash memory is widely used in consumer electronics products, such as cell-phones and music players, and is increasingly displacing hard disk drives as the primary stor...
Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R....
FPL
2003
Springer
120views Hardware» more  FPL 2003»
13 years 9 months ago
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms
The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implem...
Konstantinos Tatas, K. Siozios, Dimitrios Soudris,...
PPOPP
2003
ACM
13 years 9 months ago
Factorization with morton-ordered quadtree matrices for memory re-use and parallelism
Quadtree matrices using Morton-order storage provide natural blocking on every level of a memory hierarchy. Writing the natural recursive algorithms to take advantage of this bloc...
Jeremy D. Frens, David S. Wise
FOCS
2003
IEEE
13 years 9 months ago
The Cost of Cache-Oblivious Searching
This paper gives tight bounds on the cost of cache-oblivious searching. The paper shows that no cache-oblivious search structure can guarantee a search performance of fewer than l...
Michael A. Bender, Gerth Stølting Brodal, R...
VLDB
2004
ACM
143views Database» more  VLDB 2004»
13 years 9 months ago
Clotho: Decoupling memory page layout from storage organization
As database application performance depends on the utilization of the memory hierarchy, smart data placement plays a central role in increasing locality and in improving memory ut...
Minglong Shao, Jiri Schindler, Steven W. Schlosser...
SIGMETRICS
2005
ACM
120views Hardware» more  SIGMETRICS 2005»
13 years 10 months ago
Automatic measurement of memory hierarchy parameters
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
Kamen Yotov, Keshav Pingali, Paul Stodghill
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
13 years 10 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
WCAE
2006
ACM
13 years 10 months ago
Web memory hierarchy learning and research environment
Learning the various structures and levels of memory hierarchy by means of conventional procedures is a complex subject. A memory hierarchy environment (Web-MHE) was proposed and ...
José Leandro D. Mendes, Luiza M. N. Coutinh...
SAC
2006
ACM
13 years 10 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
ASPDAC
2006
ACM
126views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A novel instruction scratchpad memory optimization method based on concomitance metric
Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated tha...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...