ISCAS
2003
IEEE
13 years 9 months ago
2003
IEEE
To increase the bandwidth of synchronous memories that are widely adopted for high performance memory systems, a predictive mode control scheme is proposed to reduce memory latenc...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
ASPLOS
2006
ACM
13 years 10 months ago
2006
ACM
Prefetching in shared-memory multiprocessor systems is an increasingly difficult problem. As system designs grow to incorporate larger numbers of faster processors, memory latency...
IPPS
2007
IEEE
13 years 10 months ago
2007
IEEE
Search-based graph queries, such as finding short paths and isomorphic subgraphs, are dominated by memory latency. If input graphs can be partitioned appropriately, large cluster...
DAC
2009
ACM
14 years 5 months ago
2009
ACM
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...