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    ASPDAC
    2012
    ACM
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    An integrated and automated memory optimization flow for FPGA behavioral synthesis
    12 years 13 days ago
    An integrated and automated memory optimization flow for FPGA behavioral synthesis
    Download  cadlab.cs.ucla.edu
    Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
    Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
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