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JOCN
2010
79views more  JOCN 2010»
12 years 10 months ago
Neural Activity in the Hippocampus and Perirhinal Cortex during Encoding Is Associated with the Durability of Episodic Memory
Studies examining medial temporal lobe (MTL) involvement in memory formation typically assess memory performance after a single, short delay. Thus, the relationship between MTL en...
Valerie A. Carr, Indre V. Viskontas, Stephen A. En...
CGF
2008
125views more  CGF 2008»
13 years 3 months ago
Interactive Visualization for Memory Reference Traces
We present the Memory Trace Visualizer (MTV), a tool that provides interactive visualization and analysis of the sequence of memory operations performed by a program as it runs. A...
A. N. M. Imroz Choudhury, Kristin C. Potter, Steve...
MASCOTS
2004
13 years 5 months ago
Mining Performance Data from Sampled Event Traces
The prominent role of the memory hierarchy as one of the major bottlenecks in achieving good program performance has motivated the search for ways of capturing the memory performa...
Ricardo Portillo, Diana Villa, Patricia J. Teller,...
CLUSTER
2004
IEEE
13 years 7 months ago
Predicting memory-access cost based on data-access patterns
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
Surendra Byna, Xian-He Sun, William Gropp, Rajeev ...
SIGMETRICS
1996
ACM
118views Hardware» more  SIGMETRICS 1996»
13 years 7 months ago
Integrating Performance Monitoring and Communication in Parallel Computers
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
Margaret Martonosi, David Ofelt, Mark Heinrich
DATE
1997
IEEE
75views Hardware» more  DATE 1997»
13 years 7 months ago
Using constraint logic programming in memory synthesis for general purpose computers
In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory ...
Renate Beckmann, Jürgen Herrmann
IPPS
2002
IEEE
13 years 8 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
EMSOFT
2004
Springer
13 years 9 months ago
An experimental analysis of the effect of the operating system on memory performance in embedded multimedia computing
As embedded systems grow in size and complexity, an operating system has become essential to simplify the design of system software, for which more accurate analysis of its impact...
Sangsoo Park, Yonghee Lee, Heonshik Shin
ICPADS
2006
IEEE
13 years 9 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...