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    2008
    ACM
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    Efficiency and scalability of barrier synchronization on NoC based many-core architectures
    13 years 6 months ago
    Efficiency and scalability of barrier synchronization on NoC based many-core architectures
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    Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
    Oreste Villa, Gianluca Palermo, Cristina Silvano
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