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    ICCAD
    2008
    IEEE
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    Overlay aware interconnect and timing variation modeling for double patterning technology
    14 years 1 months ago
    Overlay aware interconnect and timing variation modeling for double patterning technology
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    — As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
    Jae-Seok Yang, David Z. Pan
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