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MICRO
1999
IEEE
91views Hardware» more  MICRO 1999»
10 years 6 months ago
The Use of Multithreading for Exception Handling
Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi
MICRO
1999
IEEE
100views Hardware» more  MICRO 1999»
10 years 6 months ago
A Superscalar 3D Graphics Engine
3D graphics performance is increasing faster than any other computing application. Almost all PC systems now include 3D graphics accelerators for games, CAD, or visualization appl...
Andrew Wolfe, Derek B. Noonburg
MICRO
1999
IEEE
104views Hardware» more  MICRO 1999»
10 years 6 months ago
Control Independence in Trace Processors
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
Eric Rotenberg, James E. Smith
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
10 years 6 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
MICRO
1999
IEEE
138views Hardware» more  MICRO 1999»
10 years 6 months ago
Dynamic 3D Graphics Workload Characterization and the Architectural Implications
Although PC-class 3D graphics hardware has made significant strides in the last several years, the underlying architectural design principles are still generally considered as a b...
Tulika Mitra, Tzi-cker Chiueh
MICRO
1999
IEEE
131views Hardware» more  MICRO 1999»
10 years 6 months ago
Value Prediction for Speculative Multithreaded Architectures
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
Pedro Marcuello, Jordi Tubella, Antonio Gonz&aacut...
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
10 years 6 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve
MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
10 years 6 months ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
10 years 6 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
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