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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
MICRO
2002
IEEE
119views Hardware» more  MICRO 2002»
13 years 5 months ago
Microarchitectural support for precomputation microthreads
Research has shown that precomputation microthreads can be useful for improving branch prediction and prefetching. However, it is not obvious how to provide the necessary microarc...
Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale ...
MICRO
2002
IEEE
159views Hardware» more  MICRO 2002»
13 years 10 months ago
Master/slave speculative parallelization
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution ...
Craig B. Zilles, Gurindar S. Sohi
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
13 years 10 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
13 years 10 months ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...
MICRO
2002
IEEE
100views Hardware» more  MICRO 2002»
13 years 10 months ago
Microarchitectural exploration with Liberty
To find the best designs, architects must rapidly simulate many design alternatives and have confidence in the results. Unfortunately, the most prevalent simulator construction ...
Manish Vachharajani, Neil Vachharajani, David A. P...
MICRO
2002
IEEE
109views Hardware» more  MICRO 2002»
13 years 10 months ago
Using modern graphics architectures for general-purpose computing: a framework and analysis
Recently, graphics hardware architectures have begun to emphasize versatility, offering rich new ways to programmatically reconfigure the graphics pipeline. In this paper, we exp...
Chris J. Thompson, Sahngyun Hahn, Mark Oskin
MICRO
2002
IEEE
124views Hardware» more  MICRO 2002»
13 years 10 months ago
Optimizing pipelines for power and performance
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
Viji Srinivasan, David Brooks, Michael Gschwind, P...
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
13 years 10 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
13 years 10 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi