MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
CMPs enable simultaneous execution of multiple applications on the same platforms that share cache resources. Diversity in the cache access patterns of these simultaneously execut...
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...