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MICRO
2009
IEEE
222views Hardware» more  MICRO 2009»
13 years 10 months ago
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
Heterogeneous multiprocessors are growingly important in the multi-core era due to their potential for high performance and energy efficiency. In order for software to fully real...
Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
13 years 10 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
13 years 10 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
MICRO
2009
IEEE
507views Hardware» more  MICRO 2009»
13 years 10 months ago
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure on...
Moinuddin K. Qureshi, John Karidis, Michele France...
MICRO
2009
IEEE
144views Hardware» more  MICRO 2009»
13 years 10 months ago
Characterizing flash memory: anomalies, observations, and applications
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, ...
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
13 years 10 months ago
Improving memory bank-level parallelism in the presence of prefetching
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N...
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
13 years 10 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...
MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
13 years 10 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
MICRO
2009
IEEE
128views Hardware» more  MICRO 2009»
13 years 10 months ago
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity...
Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramach...
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
13 years 10 months ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri