MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Building an optimising compiler is a difficult and time consuming task which must be repeated for each generation of a microprocessor. As the underlying microarchitecture changes...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...