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PATMOS
2005
Springer
10 years 6 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
VLSID
2001
IEEE
98views VLSI» more  VLSID 2001»
11 years 1 months ago
Complexity Of Minimum-Delay Gate Resizing
Supratik Chakraborty, Rajeev Murgai
books