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MASCOTS
1994
9 years 2 months ago
The Feasibility of Using Compression to Increase Memory System Performance
We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression e ectively incre...
Jenlong Wang, Russell W. Quong
ISSS
1996
IEEE
125views Hardware» more  ISSS 1996»
9 years 5 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
Hiroyuki Tomiyama, Hiroto Yasuura
SAC
2004
ACM
9 years 7 months ago
GD-GhOST: a goal-oriented self-tuning caching algorithm
A popular solution to internet performance problems is the widespread caching of data. Many caching algorithms have been proposed in the literature, most attempting to optimize fo...
Ganesh Santhanakrishnan, Ahmed Amer, Panos K. Chry...
ACMMSP
2004
ACM
131views Hardware» more  ACMMSP 2004»
9 years 7 months ago
Reuse-distance-based miss-rate prediction on a per instruction basis
Feedback-directed optimization has become an increasingly important tool in designing and building optimizing compilers. Recently, reuse-distance analysis has shown much promise i...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
IEEEPACT
2005
IEEE
9 years 7 months ago
Instruction Based Memory Distance Analysis and its Application
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...
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